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cuda : utilize tensor cores with multiple GPU devices
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@ -6361,7 +6361,7 @@ inline void ggml_cuda_op_mul_mat_cublas(
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const int compute_capability = g_compute_capabilities[id];
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if (compute_capability >= CC_VOLTA && (src0->type == GGML_TYPE_F16 || ggml_is_quantized(src0->type)) && ggml_is_contiguous(src0) && row_diff == src0->ne[1]) {
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if (compute_capability >= CC_VOLTA && (src0->type == GGML_TYPE_F16 || ggml_is_quantized(src0->type)) && ggml_is_contiguous(src0)) {
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// convert src0 and src1 to fp16, multiply as fp16, convert dst to fp32
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half * src0_as_f16 = nullptr;
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size_t src0_as = 0;
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@ -6386,7 +6386,7 @@ inline void ggml_cuda_op_mul_mat_cublas(
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const half * src1_ptr = src1->type == GGML_TYPE_F16 ? (const half *) src1_ddq_i : src1_as_f16;
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size_t dst_as = 0;
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half * dst_f16 = (half *) ggml_cuda_pool_malloc(row_diff*src1_ncols * sizeof(half), &dst_as);
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half * dst_f16 = (half *) ggml_cuda_pool_malloc(ldc*src1_ncols * sizeof(half), &dst_as);
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const half alpha_f16 = 1.0f;
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const half beta_f16 = 0.0f;
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@ -6402,7 +6402,7 @@ inline void ggml_cuda_op_mul_mat_cublas(
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CUBLAS_GEMM_DEFAULT_TENSOR_OP));
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const to_fp32_cuda_t to_fp32_cuda = ggml_get_to_fp32_cuda(GGML_TYPE_F16);
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to_fp32_cuda(dst_f16, dst_dd_i, row_diff*src1_ncols, stream);
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to_fp32_cuda(dst_f16, dst_dd_i, ldc*src1_ncols, stream);
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ggml_cuda_pool_free(dst_f16, dst_as);
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