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metal : add kernel_get_rows_i32
ggml-ci
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@ -87,6 +87,7 @@ struct ggml_metal_context {
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GGML_METAL_DECL_KERNEL(get_rows_q4_K);
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GGML_METAL_DECL_KERNEL(get_rows_q4_K);
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GGML_METAL_DECL_KERNEL(get_rows_q5_K);
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GGML_METAL_DECL_KERNEL(get_rows_q5_K);
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GGML_METAL_DECL_KERNEL(get_rows_q6_K);
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GGML_METAL_DECL_KERNEL(get_rows_q6_K);
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GGML_METAL_DECL_KERNEL(get_rows_i32);
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GGML_METAL_DECL_KERNEL(rms_norm);
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GGML_METAL_DECL_KERNEL(rms_norm);
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GGML_METAL_DECL_KERNEL(group_norm);
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GGML_METAL_DECL_KERNEL(group_norm);
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GGML_METAL_DECL_KERNEL(norm);
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GGML_METAL_DECL_KERNEL(norm);
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@ -377,6 +378,7 @@ struct ggml_metal_context * ggml_metal_init(int n_cb) {
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GGML_METAL_ADD_KERNEL(get_rows_q4_K);
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GGML_METAL_ADD_KERNEL(get_rows_q4_K);
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GGML_METAL_ADD_KERNEL(get_rows_q5_K);
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GGML_METAL_ADD_KERNEL(get_rows_q5_K);
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GGML_METAL_ADD_KERNEL(get_rows_q6_K);
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GGML_METAL_ADD_KERNEL(get_rows_q6_K);
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GGML_METAL_ADD_KERNEL(get_rows_i32);
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GGML_METAL_ADD_KERNEL(rms_norm);
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GGML_METAL_ADD_KERNEL(rms_norm);
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GGML_METAL_ADD_KERNEL(group_norm);
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GGML_METAL_ADD_KERNEL(group_norm);
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GGML_METAL_ADD_KERNEL(norm);
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GGML_METAL_ADD_KERNEL(norm);
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@ -499,6 +501,7 @@ void ggml_metal_free(struct ggml_metal_context * ctx) {
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GGML_METAL_DEL_KERNEL(get_rows_q4_K);
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GGML_METAL_DEL_KERNEL(get_rows_q4_K);
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GGML_METAL_DEL_KERNEL(get_rows_q5_K);
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GGML_METAL_DEL_KERNEL(get_rows_q5_K);
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GGML_METAL_DEL_KERNEL(get_rows_q6_K);
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GGML_METAL_DEL_KERNEL(get_rows_q6_K);
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GGML_METAL_DEL_KERNEL(get_rows_i32);
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GGML_METAL_DEL_KERNEL(rms_norm);
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GGML_METAL_DEL_KERNEL(rms_norm);
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GGML_METAL_DEL_KERNEL(group_norm);
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GGML_METAL_DEL_KERNEL(group_norm);
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GGML_METAL_DEL_KERNEL(norm);
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GGML_METAL_DEL_KERNEL(norm);
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@ -1978,6 +1981,7 @@ void ggml_metal_graph_compute(
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case GGML_TYPE_Q4_K: [encoder setComputePipelineState:ctx->pipeline_get_rows_q4_K]; break;
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case GGML_TYPE_Q4_K: [encoder setComputePipelineState:ctx->pipeline_get_rows_q4_K]; break;
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case GGML_TYPE_Q5_K: [encoder setComputePipelineState:ctx->pipeline_get_rows_q5_K]; break;
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case GGML_TYPE_Q5_K: [encoder setComputePipelineState:ctx->pipeline_get_rows_q5_K]; break;
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case GGML_TYPE_Q6_K: [encoder setComputePipelineState:ctx->pipeline_get_rows_q6_K]; break;
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case GGML_TYPE_Q6_K: [encoder setComputePipelineState:ctx->pipeline_get_rows_q6_K]; break;
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case GGML_TYPE_I32: [encoder setComputePipelineState:ctx->pipeline_get_rows_i32]; break;
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default: GGML_ASSERT(false && "not implemented");
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default: GGML_ASSERT(false && "not implemented");
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}
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}
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@ -3829,6 +3829,35 @@ kernel void kernel_get_rows_f16(
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}
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}
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}
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}
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kernel void kernel_get_rows_i32(
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device const void * src0,
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device const char * src1,
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device int32_t * dst,
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constant int64_t & ne00,
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constant uint64_t & nb01,
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constant uint64_t & nb02,
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constant int64_t & ne10,
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constant uint64_t & nb10,
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constant uint64_t & nb11,
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constant uint64_t & nb1,
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constant uint64_t & nb2,
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uint3 tgpig[[threadgroup_position_in_grid]],
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uint tiitg[[thread_index_in_threadgroup]],
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uint3 tptg [[threads_per_threadgroup]]) {
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const int64_t i10 = tgpig.x;
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const int64_t i11 = tgpig.y;
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const int64_t r = ((device int32_t *) ((device char *) src1 + i11*nb11 + i10*nb10))[0];
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const int64_t i02 = i11;
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for (int ind = tiitg; ind < ne00; ind += tptg.x) {
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((device int32_t *) ((device char *) dst + i11*nb2 + i10*nb1))[ind] =
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((device int32_t *) ((device char *) src0 + r*nb01 + i02*nb02))[ind];
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}
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}
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#define BLOCK_SIZE_M 64 // 8 simdgroup matrices from matrix A
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#define BLOCK_SIZE_M 64 // 8 simdgroup matrices from matrix A
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#define BLOCK_SIZE_N 32 // 4 simdgroup matrices from matrix B
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#define BLOCK_SIZE_N 32 // 4 simdgroup matrices from matrix B
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#define BLOCK_SIZE_K 32
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#define BLOCK_SIZE_K 32
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