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CUDA: faster q8_0 -> f16 dequantization (#4895)
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ggml-cuda.cu
57
ggml-cuda.cu
@ -523,6 +523,8 @@ static_assert(sizeof(block_iq2_xs) == sizeof(ggml_fp16_t) + QK_K/8*sizeof(uint16
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#define CUDA_ACC_BLOCK_SIZE 256
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#define CUDA_IM2COL_BLOCK_SIZE 256
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#define CUDA_Q8_0_NE_ALIGN 2048
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// dmmv = dequantize_mul_mat_vec
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#ifndef GGML_CUDA_DMMV_X
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#define GGML_CUDA_DMMV_X 32
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@ -2327,6 +2329,45 @@ static __global__ void convert_unary(const void * __restrict__ vx, dst_t * __res
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y[i] = x[i];
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}
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template <bool need_check>
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static __global__ void dequantize_block_q8_0_f16(const void * __restrict__ vx, half * __restrict__ y, const int k) {
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#if __CUDA_ARCH__ >= CC_PASCAL
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constexpr int nint = CUDA_Q8_0_NE_ALIGN/sizeof(int) + WARP_SIZE;
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const int i0 = CUDA_Q8_0_NE_ALIGN*blockIdx.x;
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const int * x0 = ((int *) vx) + blockIdx.x * nint;
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half2 * y2 = (half2 *) (y + i0);
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__shared__ int vals[nint];
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#pragma unroll
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for (int ix0 = 0; ix0 < nint; ix0 += WARP_SIZE) {
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if (need_check && i0*sizeof(block_q8_0)/QK8_0 + sizeof(int)*(ix0 + threadIdx.x) >= k*sizeof(block_q8_0)/QK8_0) {
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break;
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}
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const int ix = ix0 + threadIdx.x;
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vals[ix] = x0[ix];
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}
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#pragma unroll
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for (int iy = 0; iy < CUDA_Q8_0_NE_ALIGN; iy += 2*WARP_SIZE) {
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if (need_check && i0 + iy + 2*threadIdx.x >= k) {
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return;
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}
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const half * b0 = ((const half *) vals) + (sizeof(block_q8_0)/sizeof(half)) * ((iy + 2*threadIdx.x)/QK8_0);
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const half d = *b0;
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const char2 qs = ((const char2 *) (b0 + 1))[threadIdx.x % (QK8_0/2)];
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y2[iy/2 + threadIdx.x] = __hmul2(make_half2(qs.x, qs.y), __half2half2(d));
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}
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#else
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(void) vx; (void) y; (void) k;
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bad_arch();
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#endif // __CUDA_ARCH__ >= CC_PASCAL
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}
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// VDR = vec dot ratio, how many contiguous integers each thread processes when the vec dot kernel is called
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// MMVQ = mul_mat_vec_q, MMQ = mul_mat_q
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@ -6181,6 +6222,17 @@ static void dequantize_block_cuda(const void * __restrict__ vx, dst_t * __restri
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dequantize_block<qk, qr, dequantize_kernel><<<num_blocks, CUDA_DEQUANTIZE_BLOCK_SIZE, 0, stream>>>(vx, y, k);
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}
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static void dequantize_block_q8_0_f16_cuda(const void * __restrict__ vx, half * __restrict__ y, const int k, cudaStream_t stream) {
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const int num_blocks = (k + CUDA_Q8_0_NE_ALIGN - 1) / CUDA_Q8_0_NE_ALIGN;
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if (k % CUDA_Q8_0_NE_ALIGN == 0) {
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const bool need_check = false;
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dequantize_block_q8_0_f16<need_check><<<num_blocks, WARP_SIZE, 0, stream>>>(vx, y, k);
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} else {
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const bool need_check = true;
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dequantize_block_q8_0_f16<need_check><<<num_blocks, WARP_SIZE, 0, stream>>>(vx, y, k);
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}
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}
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template<typename dst_t>
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static void dequantize_row_q2_K_cuda(const void * vx, dst_t * y, const int k, cudaStream_t stream) {
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const int nb = k / QK_K;
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@ -6246,6 +6298,7 @@ static void convert_unary_cuda(const void * __restrict__ vx, dst_t * __restrict_
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}
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static to_fp16_cuda_t ggml_get_to_fp16_cuda(ggml_type type) {
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int id;
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switch (type) {
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case GGML_TYPE_Q4_0:
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return dequantize_block_cuda<QK4_0, QR4_0, dequantize_q4_0>;
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@ -6256,6 +6309,10 @@ static to_fp16_cuda_t ggml_get_to_fp16_cuda(ggml_type type) {
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case GGML_TYPE_Q5_1:
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return dequantize_block_cuda<QK5_1, QR5_1, dequantize_q5_1>;
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case GGML_TYPE_Q8_0:
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CUDA_CHECK(cudaGetDevice(&id));
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if (g_device_caps[id].cc >= CC_PASCAL) {
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return dequantize_block_q8_0_f16_cuda;
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}
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return dequantize_block_cuda<QK8_0, QR8_0, dequantize_q8_0>;
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case GGML_TYPE_Q2_K:
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return dequantize_row_q2_K_cuda;
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