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CUDA: fix --split-mode row race condition (#9413)
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@ -26,7 +26,11 @@ void ggml_cuda_op_mul_mat_q(
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// nrows_dst == nrows of the matrix that the kernel writes into
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const int64_t nrows_dst = id == ctx.device ? ne0 : row_diff;
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const mmq_args args = {src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, stride00, src1_padded_row_size, src1_ncols, ne11, nrows_dst};
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// The stream-k decomposition is only faster for recent NVIDIA GPUs.
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// Also its fixup needs to allocate a temporary buffer in the memory pool.
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// There are multiple parallel CUDA streams for src1_ncols != ne11 which would introduce a race condition for this buffer.
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const bool use_stream_k = compute_capability >= CC_VOLTA && compute_capability < CC_OFFSET_AMD && src1_ncols == ne11;
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const mmq_args args = {src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, stride00, src1_padded_row_size, src1_ncols, ne11, nrows_dst, use_stream_k};
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switch (src0->type) {
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case GGML_TYPE_Q4_0:
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@ -2742,6 +2742,7 @@ struct mmq_args {
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int64_t ne00; int64_t ne01; int64_t stride01;
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int64_t ne10; int64_t ne11; int64_t stride11;
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int64_t ne0;
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bool use_stream_k;
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};
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template<ggml_type type>
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@ -2777,8 +2778,7 @@ static void launch_mul_mat_q(ggml_backend_cuda_context & ctx, const mmq_args & a
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const int ntx = (args.ne11 + mmq_x - 1) / mmq_x;
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const dim3 block_nums_xy_tiling(nty, ntx, 1);
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const bool use_stream_k = cc >= CC_VOLTA && cc < CC_OFFSET_AMD;
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if (!use_stream_k) {
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if (!args.use_stream_k) {
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if (args.ne01 % mmq_y == 0) {
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constexpr bool need_check = false;
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mul_mat_q<type, mmq_x, MMQ_NWARPS, need_check><<<block_nums_xy_tiling, block_dims, shmem, stream>>>
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