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https://github.com/ggerganov/llama.cpp.git
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ggml : add loongarch lsx and lasx support (#6454)
* add loongarch lsx and lasx optimize code * Add loongarch compilation support to makefile * revert stb_image.h * opt bytes_from_nibbles_32 and sum_i16_pairs_float * fix undeclared * format code * update * update 2 --------- Co-authored-by: Jinyang He <hejinyang@loongson.cn>
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junchao-loongson
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@ -134,6 +134,8 @@ set(LLAMA_SCHED_MAX_COPIES "4" CACHE STRING "llama: max input copies for pipeli
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option(LLAMA_BUILD_TESTS "llama: build tests" ${LLAMA_STANDALONE})
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option(LLAMA_BUILD_EXAMPLES "llama: build examples" ${LLAMA_STANDALONE})
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option(LLAMA_BUILD_SERVER "llama: build server example" ON)
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option(LLAMA_LASX "llama: enable lasx" ON)
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option(LLAMA_LSX "llama: enable lsx" ON)
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# add perf arguments
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option(LLAMA_PERF "llama: enable perf" OFF)
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@ -1108,6 +1110,17 @@ elseif (${CMAKE_SYSTEM_PROCESSOR} MATCHES "ppc64")
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list(APPEND ARCH_FLAGS -mcpu=native -mtune=native)
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#TODO: Add targets for Power8/Power9 (Altivec/VSX) and Power10(MMA) and query for big endian systems (ppc64/le/be)
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endif()
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elseif (${CMAKE_SYSTEM_PROCESSOR} MATCHES "loongarch64")
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message(STATUS "loongarch64 detected")
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list(APPEND ARCH_FLAGS -march=loongarch64)
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if (LLAMA_LASX)
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list(APPEND ARCH_FLAGS -mlasx)
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endif()
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if (LLAMA_LSX)
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list(APPEND ARCH_FLAGS -mlsx)
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endif()
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else()
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message(STATUS "Unknown architecture")
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endif()
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5
Makefile
5
Makefile
@ -379,6 +379,11 @@ ifneq ($(filter ppc64le%,$(UNAME_M)),)
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CUDA_POWER_ARCH = 1
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endif
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ifneq ($(filter loongarch64%,$(UNAME_M)),)
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MK_CFLAGS += -mlasx
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MK_CXXFLAGS += -mlasx
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endif
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else
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MK_CFLAGS += -march=rv64gcv -mabi=lp64d
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MK_CXXFLAGS += -march=rv64gcv -mabi=lp64d
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28
ggml-impl.h
28
ggml-impl.h
@ -455,6 +455,34 @@ static inline ggml_fp16_t ggml_compute_fp32_to_fp16(float f) {
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#include <riscv_vector.h>
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#endif
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#if defined(__loongarch64)
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#if defined(__loongarch_asx)
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#include <lasxintrin.h>
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#endif
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#if defined(__loongarch_sx)
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#include <lsxintrin.h>
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#endif
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#endif
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#if defined(__loongarch_asx)
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typedef union {
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int32_t i;
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float f;
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} ft_union;
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/* float type data load instructions */
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static __m128 __lsx_vreplfr2vr_s(float val) {
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ft_union fi_tmpval = {.f = val};
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return (__m128)__lsx_vreplgr2vr_w(fi_tmpval.i);
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}
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static __m256 __lasx_xvreplfr2vr_s(float val) {
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ft_union fi_tmpval = {.f = val};
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return (__m256)__lasx_xvreplgr2vr_w(fi_tmpval.i);
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}
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#endif
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#ifdef __F16C__
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#ifdef _MSC_VER
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2089
ggml-quants.c
2089
ggml-quants.c
File diff suppressed because it is too large
Load Diff
189
ggml.c
189
ggml.c
@ -1523,6 +1523,195 @@ static inline void __sse_f16x4_store(ggml_fp16_t *x, __m128 y) {
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#define GGML_F16_VEC_MUL GGML_F32Cx4_MUL
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#define GGML_F16_VEC_REDUCE GGML_F32Cx4_REDUCE
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#elif defined(__loongarch_asx)
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#define GGML_SIMD
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// F32 LASX
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#define GGML_F32_STEP 32
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#define GGML_F32_EPR 8
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#define GGML_F32x8 __m256
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#define GGML_F32x8_ZERO (__m256)__lasx_xvldi(0)
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#define GGML_F32x8_SET1(x) (__m256)__lasx_xvreplfr2vr_s((x))
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#define GGML_F32x8_LOAD(x) (__m256)__lasx_xvld((x), 0)
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#define GGML_F32x8_STORE(x,y) __lasx_xvst((y), (x), 0)
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#define GGML_F32x8_FMA(a, b, c) __lasx_xvfmadd_s(b, c, a)
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#define GGML_F32x8_ADD __lasx_xvfadd_s
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#define GGML_F32x8_MUL __lasx_xvfmul_s
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#define GGML_F32x8_REDUCE(res, x) \
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do { \
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int offset = GGML_F32_ARR >> 1; \
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for (int i = 0; i < offset; ++i) { \
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x[i] = __lasx_xvfadd_s(x[i], x[offset+i]); \
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} \
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offset >>= 1; \
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for (int i = 0; i < offset; ++i) { \
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x[i] = __lasx_xvfadd_s(x[i], x[offset+i]); \
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} \
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offset >>= 1; \
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for (int i = 0; i < offset; ++i) { \
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x[i] = __lasx_xvfadd_s(x[i], x[offset+i]); \
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} \
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float *tmp_p = (float *)&x[0]; \
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res = tmp_p[0] + tmp_p[1] + tmp_p[2] + tmp_p[3] + tmp_p[4] + tmp_p[5] + tmp_p[6] + tmp_p[7]; \
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} while (0)
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// TODO: is this optimal ?
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#define GGML_F32_VEC GGML_F32x8
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#define GGML_F32_VEC_ZERO GGML_F32x8_ZERO
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#define GGML_F32_VEC_SET1 GGML_F32x8_SET1
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#define GGML_F32_VEC_LOAD GGML_F32x8_LOAD
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#define GGML_F32_VEC_STORE GGML_F32x8_STORE
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#define GGML_F32_VEC_FMA GGML_F32x8_FMA
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#define GGML_F32_VEC_ADD GGML_F32x8_ADD
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#define GGML_F32_VEC_MUL GGML_F32x8_MUL
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#define GGML_F32_VEC_REDUCE GGML_F32x8_REDUCE
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// F16 LASX
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#define GGML_F16_STEP 32
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#define GGML_F16_EPR 8
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// F16 arithmetic is not supported by AVX, so we use F32 instead
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#define GGML_F32Cx8 __m256
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#define GGML_F32Cx8_ZERO (__m256)__lasx_xvldi(0)
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#define GGML_F32Cx8_SET1(x) (__m256)__lasx_xvreplgr2vr_w((x))
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static inline __m256 __lasx_f32cx8_load(ggml_fp16_t *x) {
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float tmp[8];
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for (int i = 0; i < 8; i++) {
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tmp[i] = GGML_FP16_TO_FP32(x[i]);
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}
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return (__m256)__lasx_xvld(tmp, 0);
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}
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static inline void __lasx_f32cx8_store(ggml_fp16_t *x, __m256 y) {
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float arr[8];
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__lasx_xvst(y, arr, 0);
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for (int i = 0; i < 8; i++)
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x[i] = GGML_FP32_TO_FP16(arr[i]);
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}
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#define GGML_F32Cx8_LOAD(x) __lasx_f32cx8_load(x)
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#define GGML_F32Cx8_STORE(x, y) __lasx_f32cx8_store(x, y)
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#define GGML_F32Cx8_FMA GGML_F32x8_FMA
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#define GGML_F32Cx8_ADD __lasx_xvfadd_s
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#define GGML_F32Cx8_MUL __lasx_xvfmul_s
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#define GGML_F32Cx8_REDUCE GGML_F32x8_REDUCE
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#define GGML_F16_VEC GGML_F32Cx8
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#define GGML_F16_VEC_ZERO GGML_F32Cx8_ZERO
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#define GGML_F16_VEC_SET1 GGML_F32Cx8_SET1
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#define GGML_F16_VEC_LOAD(p, i) GGML_F32Cx8_LOAD(p)
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#define GGML_F16_VEC_STORE(p, r, i) GGML_F32Cx8_STORE(p, r[i])
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#define GGML_F16_VEC_FMA GGML_F32Cx8_FMA
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#define GGML_F16_VEC_ADD GGML_F32Cx8_ADD
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#define GGML_F16_VEC_MUL GGML_F32Cx8_MUL
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#define GGML_F16_VEC_REDUCE GGML_F32Cx8_REDUCE
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#elif defined(__loongarch_sx)
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#define GGML_SIMD
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// F32 LSX
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#define GGML_F32_STEP 32
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#define GGML_F32_EPR 4
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#define GGML_F32x4 __m128
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#define GGML_F32x4_ZERO __lsx_vldi(0)
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#define GGML_F32x4_SET1(x) __lsx_vinsgr2vr_w(__lsx_vldi(0),(x), 0)
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#define GGML_F32x4_LOAD(x) __lsx_vld((x), 0)
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#define GGML_F32x4_STORE((x),(y)) __lsx_vst((y), (x), 0)
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#define GGML_F32x4_FMA(a, b, c) __lsx_vfmadd_s(b, c, a)
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#define GGML_F32x4_ADD __lsx_vfadd_s
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#define GGML_F32x4_MUL __lsx_vfmul_s
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#define GGML_F32x4_REDUCE(res, x) \
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{ \
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int offset = GGML_F32_ARR >> 1; \
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for (int i = 0; i < offset; ++i) { \
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x[i] = __lsx_vfadd_s(x[i], x[offset+i]); \
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} \
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offset >>= 1; \
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for (int i = 0; i < offset; ++i) { \
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x[i] = __lsx_vfadd_s(x[i], x[offset+i]); \
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} \
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offset >>= 1; \
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for (int i = 0; i < offset; ++i) { \
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x[i] = __lsx_vfadd_s(x[i], x[offset+i]); \
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} \
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__m128i tmp = __lsx_vsrli_d((__m128i)x[0], 32); \
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tmp = (__m128i)__lsx_vfadd_s((__m128)tmp, x[0]); \
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tmp = __lsx_vpickev_w(__lsx_vldi(0), tmp); \
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const __m128 t0 = __lsx_vshuf4i_w(tmp, 0x88); \
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tmp = __lsx_vsrli_d((__m128i)t0, 32); \
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tmp = (__m128i)__lsx_vfadd_s((__m128)tmp, t0); \
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tmp = __lsx_vpickev_w(__lsx_vldi(0), tmp); \
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res = (ggml_float) __lsx_vpickve2gr_w(__lsx_vshuf4i_w(tmp, 0x88), 0); \
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}
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#define GGML_F32_VEC GGML_F32x4
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#define GGML_F32_VEC_ZERO GGML_F32x4_ZERO
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#define GGML_F32_VEC_SET1 GGML_F32x4_SET1
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#define GGML_F32_VEC_LOAD GGML_F32x4_LOAD
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#define GGML_F32_VEC_STORE GGML_F32x4_STORE
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#define GGML_F32_VEC_FMA GGML_F32x4_FMA
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#define GGML_F32_VEC_ADD GGML_F32x4_ADD
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#define GGML_F32_VEC_MUL GGML_F32x4_MUL
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#define GGML_F32_VEC_REDUCE GGML_F32x4_REDUCE
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// F16 LSX
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#define GGML_F16_STEP 32
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#define GGML_F16_EPR 4
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static inline __m128 __lsx_f16x4_load(ggml_fp16_t *x) {
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float tmp[4];
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tmp[0] = GGML_FP16_TO_FP32(x[0]);
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tmp[1] = GGML_FP16_TO_FP32(x[1]);
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tmp[2] = GGML_FP16_TO_FP32(x[2]);
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tmp[3] = GGML_FP16_TO_FP32(x[3]);
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return __lsx_vld(tmp, 0);
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}
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static inline void __lsx_f16x4_store(ggml_fp16_t *x, __m128 y) {
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float arr[4];
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__lsx_vst(y, arr, 0);
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x[0] = GGML_FP32_TO_FP16(arr[0]);
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x[1] = GGML_FP32_TO_FP16(arr[1]);
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x[2] = GGML_FP32_TO_FP16(arr[2]);
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x[3] = GGML_FP32_TO_FP16(arr[3]);
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}
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#define GGML_F32Cx4 __m128
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#define GGML_F32Cx4_ZERO __lsx_vldi(0)
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#define GGML_F32Cx4_SET1(x) __lsx_vinsgr2vr_w(__lsx_vldi(0),(x), 0)
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#define GGML_F32Cx4_LOAD(x) __lsx_f16x4_load(x)
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#define GGML_F32Cx4_STORE(x, y) __lsx_f16x4_store(x, y)
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#define GGML_F32Cx4_FMA GGML_F32x4_FMA
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#define GGML_F32Cx4_ADD __lsx_vfadd_s
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#define GGML_F32Cx4_MUL __lsx_vfmul_s
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#define GGML_F32Cx4_REDUCE GGML_F32x4_REDUCE
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#define GGML_F16_VEC GGML_F32Cx4
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#define GGML_F16_VEC_ZERO GGML_F32Cx4_ZERO
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#define GGML_F16_VEC_SET1 GGML_F32Cx4_SET1
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#define GGML_F16_VEC_LOAD(p, i) GGML_F32Cx4_LOAD(p)
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#define GGML_F16_VEC_STORE(p, r, i) GGML_F32Cx4_STORE(p, r[i])
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#define GGML_F16_VEC_FMA GGML_F32Cx4_FMA
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#define GGML_F16_VEC_ADD GGML_F32Cx4_ADD
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#define GGML_F16_VEC_MUL GGML_F32Cx4_MUL
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#define GGML_F16_VEC_REDUCE GGML_F32Cx4_REDUCE
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#endif
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// GGML_F32_ARR / GGML_F16_ARR
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