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metal : add Q2_K implementation (#1762)
* metal : add Q2_K implementation 27.1 ms / token on M2 Max 30-core GPU, so about the same speed as Q4_0. Memory throughput is ~156 GB/s. The access pattern used in the Q2_K CUDA implementation resulted in significantly lower performance (~31 ms/token). * Fixing merge conflicts --------- Co-authored-by: Iwan Kawrakow <iwan.kawrakow@gmail.com>
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Kawrakow
GitHub
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17
ggml-metal.m
17
ggml-metal.m
@ -49,11 +49,13 @@ struct ggml_metal_context {
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GGML_METAL_DECL_KERNEL(diag_mask_inf);
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GGML_METAL_DECL_KERNEL(get_rows_f16);
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GGML_METAL_DECL_KERNEL(get_rows_q4_0);
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GGML_METAL_DECL_KERNEL(get_rows_q2_k);
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GGML_METAL_DECL_KERNEL(get_rows_q4_k);
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GGML_METAL_DECL_KERNEL(get_rows_q6_k);
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GGML_METAL_DECL_KERNEL(rms_norm);
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GGML_METAL_DECL_KERNEL(mul_mat_f16_f32);
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GGML_METAL_DECL_KERNEL(mul_mat_q4_0_f32);
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GGML_METAL_DECL_KERNEL(mul_mat_q2_k_f32);
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GGML_METAL_DECL_KERNEL(mul_mat_q4_k_f32);
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GGML_METAL_DECL_KERNEL(mul_mat_q6_k_f32);
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GGML_METAL_DECL_KERNEL(rope);
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@ -137,11 +139,13 @@ struct ggml_metal_context * ggml_metal_init(void) {
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GGML_METAL_ADD_KERNEL(diag_mask_inf);
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GGML_METAL_ADD_KERNEL(get_rows_f16);
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GGML_METAL_ADD_KERNEL(get_rows_q4_0);
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GGML_METAL_ADD_KERNEL(get_rows_q2_k);
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GGML_METAL_ADD_KERNEL(get_rows_q4_k);
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GGML_METAL_ADD_KERNEL(get_rows_q6_k);
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GGML_METAL_ADD_KERNEL(rms_norm);
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GGML_METAL_ADD_KERNEL(mul_mat_f16_f32);
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GGML_METAL_ADD_KERNEL(mul_mat_q4_0_f32);
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GGML_METAL_ADD_KERNEL(mul_mat_q2_k_f32);
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GGML_METAL_ADD_KERNEL(mul_mat_q4_k_f32);
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GGML_METAL_ADD_KERNEL(mul_mat_q6_k_f32);
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GGML_METAL_ADD_KERNEL(rope);
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@ -525,6 +529,15 @@ void ggml_metal_graph_compute(
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nth1 = 4;
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[encoder setComputePipelineState:ctx->pipeline_mul_mat_q4_0_f32];
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} break;
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case GGML_TYPE_Q2_K:
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{
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GGML_ASSERT(ne02 == 1);
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GGML_ASSERT(ne12 == 1);
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nth0 = 4;
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nth1 = 16;
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[encoder setComputePipelineState:ctx->pipeline_mul_mat_q2_k_f32];
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} break;
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case GGML_TYPE_Q4_K:
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{
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GGML_ASSERT(ne02 == 1);
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@ -570,6 +583,9 @@ void ggml_metal_graph_compute(
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if (src0t == GGML_TYPE_Q4_0) {
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[encoder setThreadgroupMemoryLength:nth0*nth1*sizeof(float) atIndex:0];
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[encoder dispatchThreadgroups:MTLSizeMake(ne01, ne11, 1) threadsPerThreadgroup:MTLSizeMake(nth0, nth1, 1)];
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} else if (src0t == GGML_TYPE_Q2_K) {
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[encoder setThreadgroupMemoryLength:nth0*nth1*sizeof(float) atIndex:0];
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[encoder dispatchThreadgroups:MTLSizeMake(ne01, 1, 1) threadsPerThreadgroup:MTLSizeMake(nth0, nth1, 1)];
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} else if (src0t == GGML_TYPE_Q4_K) {
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[encoder setThreadgroupMemoryLength:nth0*nth1*sizeof(float) atIndex:0];
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[encoder dispatchThreadgroups:MTLSizeMake(ne01, ne11, 1) threadsPerThreadgroup:MTLSizeMake(nth0, nth1, 1)];
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@ -591,6 +607,7 @@ void ggml_metal_graph_compute(
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switch (src0->type) {
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case GGML_TYPE_F16: [encoder setComputePipelineState:ctx->pipeline_get_rows_f16]; break;
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case GGML_TYPE_Q4_0: [encoder setComputePipelineState:ctx->pipeline_get_rows_q4_0]; break;
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case GGML_TYPE_Q2_K: [encoder setComputePipelineState:ctx->pipeline_get_rows_q2_k]; break;
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case GGML_TYPE_Q4_K: [encoder setComputePipelineState:ctx->pipeline_get_rows_q4_k]; break;
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case GGML_TYPE_Q6_K: [encoder setComputePipelineState:ctx->pipeline_get_rows_q6_k]; break;
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default: GGML_ASSERT(false && "not implemented");
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201
ggml-metal.metal
201
ggml-metal.metal
@ -527,6 +527,13 @@ kernel void kernel_cpy_f32_f32(
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#define QK_K 256
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typedef struct {
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uint8_t scales[QK_K/16]; // scales and mins, quantized with 4 bits
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uint8_t qs[QK_K/4]; // quants
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half d; // super-block scale for quantized scales
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half dmin; // super-block scale for quantized mins
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} block_q2_k;
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typedef struct {
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half d; // super-block scale for quantized scales
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half dmin; // super-block scale for quantized mins
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@ -555,6 +562,41 @@ static inline uchar4 get_scale_min_k4(int j, device const uint8_t * q) {
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return r;
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}
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//========================================== dequantization =============================
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static void dequantize_row_q2_k(device const block_q2_k * x, device float * y, int k) {
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assert(k % QK_K == 0);
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const int nb = k / QK_K;
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for (int i = 0; i < nb; i++) {
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const float d = x[i].d;
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const float min = x[i].dmin;
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device const uint8_t * q = x[i].qs;
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int is = 0;
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float dl, ml;
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for (int n = 0; n < QK_K; n += 128) {
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int shift = 0;
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for (int j = 0; j < 4; ++j) {
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uint8_t sc = x[i].scales[is++];
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dl = d * (sc & 0xF); ml = min * (sc >> 4);
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for (int l = 0; l < 16; ++l) *y++ = dl * ((int8_t)((q[l] >> shift) & 3)) - ml;
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sc = x[i].scales[is++];
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dl = d * (sc & 0xF); ml = min * (sc >> 4);
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for (int l = 0; l < 16; ++l) *y++ = dl * ((int8_t)((q[l+16] >> shift) & 3)) - ml;
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shift += 2;
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}
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q += 32;
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}
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}
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}
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static void dequantize_row_q4_k(device const block_q4_k * x, device float * y, int k) {
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assert(k % QK_K == 0);
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const int nb = k / QK_K;
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@ -586,12 +628,12 @@ static void dequantize_row_q6_k(device const block_q6_k * x, device float * y, i
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for (int i = 0; i < nb; i++) {
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const float d = x[i].d;
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device const uint8_t * ql = x[i].ql;
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device const uint8_t * qh = x[i].qh;
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device const int8_t * sc = x[i].scales;
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const float d = x[i].d;
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for (int n = 0; n < QK_K; n += 128) {
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for (int l = 0; l < 32; ++l) {
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int is = l/16;
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@ -612,6 +654,22 @@ static void dequantize_row_q6_k(device const block_q6_k * x, device float * y, i
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}
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}
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kernel void kernel_get_rows_q2_k(
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device const void * src0,
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device const int * src1,
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device float * dst,
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constant int64_t & ne00,
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constant uint64_t & nb01,
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constant uint64_t & nb1,
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uint tpig[[thread_position_in_grid]]) {
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const int i = tpig;
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const int r = ((device int32_t *) src1)[i];
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dequantize_row_q2_k(
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(device const block_q2_k *) ((device char *) src0 + r*nb01),
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(device float *) ((device char *) dst + i*nb1), ne00);
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}
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kernel void kernel_get_rows_q4_k(
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device const void * src0,
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device const int * src1,
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@ -628,6 +686,129 @@ kernel void kernel_get_rows_q4_k(
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(device float *) ((device char *) dst + i*nb1), ne00);
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}
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kernel void kernel_get_rows_q6_k(
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device const void * src0,
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device const int * src1,
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device float * dst,
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constant int64_t & ne00,
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constant uint64_t & nb01,
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constant uint64_t & nb1,
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uint tpig[[thread_position_in_grid]]) {
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const int i = tpig;
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const int r = ((device int32_t *) src1)[i];
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dequantize_row_q6_k(
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(device const block_q6_k *) ((device char *) src0 + r*nb01),
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(device float *) ((device char *) dst + i*nb1), ne00);
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}
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//====================================== dot products =========================
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kernel void kernel_mul_mat_q2_k_f32(
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device const void * src0,
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device const float * src1,
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device float * dst,
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constant int64_t & ne00,
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constant int64_t & ne01,
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constant uint64_t & nb00,
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constant uint64_t & nb01,
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constant uint64_t & nb02,
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constant int64_t & ne10,
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constant int64_t & ne11,
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constant uint64_t & nb10,
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constant uint64_t & nb11,
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constant uint64_t & nb12,
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constant int64_t & ne0,
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constant int64_t & ne1,
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threadgroup float * sum [[threadgroup(0)]],
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uint2 tgpig[[threadgroup_position_in_grid]],
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uint2 tpig[[thread_position_in_grid]], // we don't use this for now
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uint2 tpitg[[thread_position_in_threadgroup]],
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uint2 tptg[[threads_per_threadgroup]]) {
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const int nb = ne00/QK_K;
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const int64_t r0 = tgpig.x;
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const int64_t r1 = tgpig.y;
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device const block_q2_k * x = (device const block_q2_k *) src0 + r0*nb;
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device const float * yy = (device const float *) src1 + r1*ne10;
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const int nth = tptg.x*tptg.y;
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const int ith = tptg.y*tpitg.x + tpitg.y;
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const int tid = tpitg.y; // 0...16
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const int il = tid/4; // 0...3
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const int ir = tid%4; // 0...3
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const int ip = il/2; // 0 or 1
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const int shift1 = 4*(il%2);// 0 or 4
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const int shift2 = shift1+2;// 2 or 6
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const int n = 8;
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const int is = 4*il + (n*ir)/16;
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sum[ith] = 0.0f;
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float sumf = 0;
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for (int i = tpitg.x; i < nb; i += tptg.x) {
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device const uint8_t * q = x[i].qs + 32*ip + n*ir;
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device const uint8_t * scales = x[i].scales + is;
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uint8_t d1 = scales[0] & 0xF;
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uint8_t m1 = scales[0] >> 4;
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uint8_t d2 = scales[2] & 0xF;
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uint8_t m2 = scales[2] >> 4;
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device const float * y = yy + i*QK_K + 64*il + n*ir;
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const float dall = (float)x[i].d;
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const float dmin = (float)x[i].dmin;
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float4 s = {0.f, 0.f, 0.f, 0.f};
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for (int l = 0; l < n; ++l) {
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s[0] += y[l+ 0] * ((q[l] >> shift1) & 3); s[1] += y[l+ 0];
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s[2] += y[l+32] * ((q[l] >> shift2) & 3); s[3] += y[l+32];
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}
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sumf += dall * (s[0] * d1 + s[2] * d2) - dmin * (s[1] * m1 + s[3] * m2);
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}
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sum[ith] = sumf;
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//
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// Accumulate the sum from all threads in the threadgroup
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// This version is slightly faster than the commented out one below,
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// which I copy-pasted from ggerganov's q4_0 dot product for metal.
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//
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threadgroup_barrier(mem_flags::mem_threadgroup);
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if (ith%4 == 0) {
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for (int i = 1; i < 4; ++i) sum[ith] += sum[ith + i];
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}
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threadgroup_barrier(mem_flags::mem_threadgroup);
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if (ith%16 == 0) {
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for (int i = 4; i < 16; i += 4) sum[ith] += sum[ith + i];
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}
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threadgroup_barrier(mem_flags::mem_threadgroup);
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if (ith == 0) {
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for (int i = 16; i < nth; i += 16) sum[0] += sum[i];
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dst[r1*ne0 + r0] = sum[0];
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}
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//// accumulate the sum from all threads in the threadgroup
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//threadgroup_barrier(mem_flags::mem_threadgroup);
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//for (uint i = nth/2; i > 0; i /= 2) {
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// if (ith < i) {
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// sum[ith] += sum[ith + i];
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// }
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// threadgroup_barrier(mem_flags::mem_threadgroup);
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//}
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//if (ith == 0) {
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// dst[r1*ne0 + r0] = sum[0];
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//}
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}
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kernel void kernel_mul_mat_q4_k_f32(
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device const void * src0,
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device const float * src1,
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@ -724,22 +905,6 @@ kernel void kernel_mul_mat_q4_k_f32(
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//}
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}
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kernel void kernel_get_rows_q6_k(
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device const void * src0,
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device const int * src1,
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device float * dst,
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constant int64_t & ne00,
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constant uint64_t & nb01,
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constant uint64_t & nb1,
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uint tpig[[thread_position_in_grid]]) {
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const int i = tpig;
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const int r = ((device int32_t *) src1)[i];
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dequantize_row_q6_k(
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(device const block_q6_k *) ((device char *) src0 + r*nb01),
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(device float *) ((device char *) dst + i*nb1), ne00);
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}
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kernel void kernel_mul_mat_q6_k_f32(
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device const void * src0,
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device const float * src1,
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