mirror of
https://github.com/ggerganov/llama.cpp.git
synced 2024-09-22 21:16:20 +00:00
CUDA: use MMQ instead of cuBLAS by default (#8075)
This commit is contained in:
Johannes Gäßler
GitHub
parent
d62e4aaa02
commit
a818f3028d
@ -102,7 +102,8 @@ option(LLAMA_LLAMAFILE "llama: use llamafile SGEMM"
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option(LLAMA_CUDA "llama: use CUDA" OFF)
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option(LLAMA_CUBLAS "llama: use CUDA (deprecated, use LLAMA_CUDA)" OFF)
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option(LLAMA_CUDA_FORCE_DMMV "llama: use dmmv instead of mmvq CUDA kernels" OFF)
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option(LLAMA_CUDA_FORCE_MMQ "llama: use mmq kernels instead of cuBLAS" OFF)
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option(LLAMA_CUDA_FORCE_MMQ "llama: always use mmq kernels instead of cuBLAS" OFF)
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option(LLAMA_CUDA_FORCE_CUBLAS "llama: always use cuBLAS instead of mmq kernels" OFF)
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set(LLAMA_CUDA_DMMV_X "32" CACHE STRING "llama: x stride for dmmv CUDA kernels")
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set(LLAMA_CUDA_MMV_Y "1" CACHE STRING "llama: y block size for mmv CUDA kernels")
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option(LLAMA_CUDA_F16 "llama: use 16 bit floats for some calculations" OFF)
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@ -416,13 +417,14 @@ if (LLAMA_CUDA)
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if (NOT DEFINED CMAKE_CUDA_ARCHITECTURES)
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# 52 == lowest CUDA 12 standard
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# 60 == f16 CUDA intrinsics
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# 60 == FP16 CUDA intrinsics
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# 61 == integer CUDA intrinsics
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# 70 == compute capability at which unrolling a loop in mul_mat_q kernels is faster
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# 70 == FP16 tensor cores
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# 75 == int8 tensor cores
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if (LLAMA_CUDA_F16 OR LLAMA_CUDA_DMMV_F16)
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set(CMAKE_CUDA_ARCHITECTURES "60;61;70") # needed for f16 CUDA intrinsics
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set(CMAKE_CUDA_ARCHITECTURES "60;61;70;75")
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else()
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set(CMAKE_CUDA_ARCHITECTURES "52;61;70") # lowest CUDA 12 standard + lowest for integer intrinsics
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set(CMAKE_CUDA_ARCHITECTURES "52;61;70;75")
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#set(CMAKE_CUDA_ARCHITECTURES "OFF") # use this to compile much faster, but only F16 models work
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endif()
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endif()
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@ -447,6 +449,9 @@ if (LLAMA_CUDA)
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if (LLAMA_CUDA_FORCE_MMQ)
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add_compile_definitions(GGML_CUDA_FORCE_MMQ)
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endif()
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if (LLAMA_CUDA_FORCE_CUBLAS)
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add_compile_definitions(GGML_CUDA_FORCE_CUBLAS)
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endif()
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if (LLAMA_CUDA_NO_VMM)
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add_compile_definitions(GGML_CUDA_NO_VMM)
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endif()
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3
Makefile
3
Makefile
@ -537,6 +537,9 @@ endif # LLAMA_CUDA_FORCE_DMMV
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ifdef LLAMA_CUDA_FORCE_MMQ
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MK_NVCCFLAGS += -DGGML_CUDA_FORCE_MMQ
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endif # LLAMA_CUDA_FORCE_MMQ
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ifdef LLAMA_CUDA_FORCE_CUBLAS
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MK_NVCCFLAGS += -DGGML_CUDA_FORCE_CUBLAS
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endif # LLAMA_CUDA_FORCE_CUBLAS
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ifdef LLAMA_CUDA_DMMV_X
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MK_NVCCFLAGS += -DGGML_CUDA_DMMV_X=$(LLAMA_CUDA_DMMV_X)
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else
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@ -510,8 +510,9 @@ Building the program with BLAS support may lead to some performance improvements
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|--------------------------------|------------------------|---------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
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| LLAMA_CUDA_FORCE_DMMV | Boolean | false | Force the use of dequantization + matrix vector multiplication kernels instead of using kernels that do matrix vector multiplication on quantized data. By default the decision is made based on compute capability (MMVQ for 6.1/Pascal/GTX 1000 or higher). Does not affect k-quants. |
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| LLAMA_CUDA_DMMV_X | Positive integer >= 32 | 32 | Number of values in x direction processed by the CUDA dequantization + matrix vector multiplication kernel per iteration. Increasing this value can improve performance on fast GPUs. Power of 2 heavily recommended. Does not affect k-quants. |
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| LLAMA_CUDA_MMV_Y | Positive integer | 1 | Block size in y direction for the CUDA mul mat vec kernels. Increasing this value can improve performance on fast GPUs. Power of 2 recommended. |
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| LLAMA_CUDA_FORCE_MMQ | Boolean | false | Force the use of dequantization + matrix multiplication kernels instead of leveraging Math libraries. | |
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| LLAMA_CUDA_MMV_Y | Positive integer | 1 | Block size in y direction for the CUDA mul mat vec kernels. Increasing this value can improve performance on fast GPUs. Power of 2 recommended. |
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| LLAMA_CUDA_FORCE_MMQ | Boolean | false | Force the use of custom matrix multiplication kernels for quantized models instead of FP16 cuBLAS even if there is no int8 tensor core implementation available (affects V100, RDNA3). Speed for large batch sizes will be worse but VRAM consumption will be lower. |
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| LLAMA_CUDA_FORCE_CUBLAS | Boolean | false | Force the use of FP16 cuBLAS instead of custom matrix multiplication kernels for quantized models |
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| LLAMA_CUDA_F16 | Boolean | false | If enabled, use half-precision floating point arithmetic for the CUDA dequantization + mul mat vec kernels and for the q4_1 and q5_1 matrix matrix multiplication kernels. Can improve performance on relatively recent GPUs. |
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| LLAMA_CUDA_KQUANTS_ITER | 1 or 2 | 2 | Number of values processed per iteration and per CUDA thread for Q2_K and Q6_K quantization formats. Setting this value to 1 can improve performance for slow GPUs. |
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| LLAMA_CUDA_PEER_MAX_BATCH_SIZE | Positive integer | 128 | Maximum batch size for which to enable peer access between multiple GPUs. Peer access requires either Linux or NVLink. When using NVLink enabling peer access for larger batch sizes is potentially beneficial. |
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96
ggml-cuda.cu
96
ggml-cuda.cu
@ -152,16 +152,16 @@ static ggml_cuda_device_info ggml_cuda_init() {
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GGML_ASSERT(info.device_count <= GGML_CUDA_MAX_DEVICES);
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int64_t total_vram = 0;
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#if defined(GGML_CUDA_FORCE_MMQ)
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GGML_CUDA_LOG_INFO("%s: GGML_CUDA_FORCE_MMQ: yes\n", __func__);
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#ifdef GGML_CUDA_FORCE_MMQ
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GGML_CUDA_LOG_INFO("%s: GGML_CUDA_FORCE_MMQ: yes\n", __func__);
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#else
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GGML_CUDA_LOG_INFO("%s: GGML_CUDA_FORCE_MMQ: no\n", __func__);
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#endif
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#if defined(CUDA_USE_TENSOR_CORES)
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GGML_CUDA_LOG_INFO("%s: CUDA_USE_TENSOR_CORES: yes\n", __func__);
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GGML_CUDA_LOG_INFO("%s: GGML_CUDA_FORCE_MMQ: no\n", __func__);
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#endif // GGML_CUDA_FORCE_MMQ
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#ifdef GGML_CUDA_FORCE_CUBLAS
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GGML_CUDA_LOG_INFO("%s: GGML_CUDA_FORCE_CUBLAS: yes\n", __func__);
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#else
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GGML_CUDA_LOG_INFO("%s: CUDA_USE_TENSOR_CORES: no\n", __func__);
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#endif
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GGML_CUDA_LOG_INFO("%s: GGML_CUDA_FORCE_CUBLAS: no\n", __func__);
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#endif // GGML_CUDA_FORCE_CUBLAS
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GGML_CUDA_LOG_INFO("%s: found %d " GGML_CUDA_NAME " devices:\n", __func__, info.device_count);
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for (int id = 0; id < info.device_count; ++id) {
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int device_vmm = 0;
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@ -1873,9 +1873,17 @@ static void ggml_cuda_mul_mat_batched_cublas(ggml_backend_cuda_context & ctx, co
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static void ggml_cuda_mul_mat(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) {
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const bool split = ggml_backend_buffer_is_cuda_split(src0->buffer);
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int64_t min_compute_capability = INT_MAX;
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bool use_dequantize_mul_mat_vec = (ggml_is_quantized(src0->type) || src0->type == GGML_TYPE_F16)
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&& src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32
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&& src0->ne[0] % GGML_CUDA_DMMV_X == 0 && src1->ne[1] == 1;
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bool use_mul_mat_vec_q = ggml_is_quantized(src0->type)
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&& src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32
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&& src1->ne[1] <= MMVQ_MAX_BATCH_SIZE;
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bool use_mul_mat_q = ggml_is_quantized(src0->type)
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&& src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32;
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bool any_gpus_with_slow_fp16 = false;
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bool any_pascal_with_slow_fp16 = false;
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if (split) {
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ggml_backend_cuda_split_buffer_type_context * buft_ctx = (ggml_backend_cuda_split_buffer_type_context *) src0->buffer->buft->context;
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auto & tensor_split = buft_ctx->tensor_split;
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@ -1885,55 +1893,18 @@ static void ggml_cuda_mul_mat(ggml_backend_cuda_context & ctx, const ggml_tensor
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continue;
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}
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if (min_compute_capability > ggml_cuda_info().devices[id].cc) {
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min_compute_capability = ggml_cuda_info().devices[id].cc;
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}
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if (ggml_cuda_info().devices[id].cc == 610) {
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any_pascal_with_slow_fp16 = true;
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}
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const int cc = ggml_cuda_info().devices[id].cc;
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use_mul_mat_vec_q = use_mul_mat_vec_q && cc >= MIN_CC_DP4A;
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use_mul_mat_q = use_mul_mat_q && ggml_cuda_should_use_mmq(src0->type, cc, src1->ne[1]);
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any_gpus_with_slow_fp16 = any_gpus_with_slow_fp16 || !fast_fp16_available(cc);
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}
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} else {
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min_compute_capability = ggml_cuda_info().devices[ctx.device].cc;
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any_pascal_with_slow_fp16 = ggml_cuda_info().devices[ctx.device].cc == 610;
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const int cc = ggml_cuda_info().devices[ctx.device].cc;
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use_mul_mat_vec_q = use_mul_mat_vec_q && cc >= MIN_CC_DP4A;
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use_mul_mat_q = use_mul_mat_q && ggml_cuda_should_use_mmq(src0->type, cc, src1->ne[1]);
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any_gpus_with_slow_fp16 = any_gpus_with_slow_fp16 || !fast_fp16_available(cc);
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}
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// check data types and tensor shapes for custom matrix multiplication kernels:
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bool use_dequantize_mul_mat_vec = (ggml_is_quantized(src0->type) || src0->type == GGML_TYPE_F16)
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&& src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32
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&& src0->ne[0] % GGML_CUDA_DMMV_X == 0 && src1->ne[1] == 1;
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bool use_mul_mat_vec_q = ggml_is_quantized(src0->type)
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&& src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32
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&& src1->ne[1] <= MMVQ_MAX_BATCH_SIZE;
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bool use_mul_mat_q = ggml_cuda_supports_mmq(src0->type)
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&& src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32;
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#if defined(GGML_USE_HIPBLAS) && defined(__HIP_PLATFORM_AMD__)
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const bool fp16_performance_good = min_compute_capability >= CC_RDNA1;
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#ifdef CUDA_USE_TENSOR_CORES
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use_mul_mat_q = use_mul_mat_q && min_compute_capability < CC_RDNA3;
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#endif // CUDA_USE_TENSOR_CORES
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#else
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// fp16 performance is good on Volta or newer and on P100 (compute capability 6.0)
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const bool fp16_performance_good = min_compute_capability >= CC_PASCAL && !any_pascal_with_slow_fp16;
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// mmvq and mmq need the __dp4a instruction which on NVIDIA is only available for CC >= 6.1
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use_mul_mat_vec_q = use_mul_mat_vec_q && min_compute_capability >= MIN_CC_DP4A;
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use_mul_mat_q = use_mul_mat_q && min_compute_capability >= MIN_CC_DP4A;
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#ifdef CUDA_USE_TENSOR_CORES
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// when tensor cores are available, use them for large batch size
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// ref: https://github.com/ggerganov/llama.cpp/pull/3776
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use_mul_mat_q = use_mul_mat_q && (!fp16_performance_good || src1->ne[1] <= MMQ_MAX_BATCH_SIZE);
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#endif // CUDA_USE_TENSOR_CORES
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#endif // defined(GGML_USE_HIPBLAS) && defined(__HIP_PLATFORM_AMD__)
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// if mmvq is available it's a better choice than dmmv:
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#ifndef GGML_CUDA_FORCE_DMMV
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use_dequantize_mul_mat_vec = use_dequantize_mul_mat_vec && !use_mul_mat_vec_q;
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@ -1947,21 +1918,22 @@ static void ggml_cuda_mul_mat(ggml_backend_cuda_context & ctx, const ggml_tensor
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//printf("src0 is contiguous %d, transposed %d, type = %s, name = %s\n", ggml_is_contiguous(src0), ggml_is_transposed(src0), ggml_type_name(src0->type), src0->name);
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//printf("src1 is contiguous %d, transposed %d, type = %s, name = %s\n", ggml_is_contiguous(src1), ggml_is_transposed(src1), ggml_type_name(src1->type), src1->name);
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if (!split && !fp16_performance_good && src0->type == GGML_TYPE_F16 && ggml_is_permuted(src0) && ggml_is_permuted(src1) && src1->ne[1] == 1) {
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// KQ single-batch
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if (!split && any_gpus_with_slow_fp16 && src0->type == GGML_TYPE_F16 && ggml_is_permuted(src0) && ggml_is_permuted(src1) && src1->ne[1] == 1) {
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// FP32 precision KQ single-batch for batch size 1 without FlashAttention
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ggml_cuda_mul_mat_vec_p021(ctx, src0, src1, dst);
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} else if (!split && !fp16_performance_good && src0->type == GGML_TYPE_F16 && !ggml_is_contiguous(src0) && !ggml_is_transposed(src1) && src1->ne[1] == 1) {
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// KQV single-batch
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} else if (!split && any_gpus_with_slow_fp16 && src0->type == GGML_TYPE_F16 && !ggml_is_contiguous(src0) && !ggml_is_transposed(src1) && src1->ne[1] == 1) {
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// FP32 precision KQV single-batch for batch size 1 without FlashAttention
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ggml_cuda_mul_mat_vec_nc(ctx, src0, src1, dst);
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} else if (!split && src0->type == GGML_TYPE_F16 && (src1->type == GGML_TYPE_F16 || fp16_performance_good) && !ggml_is_transposed(src0) && !ggml_is_transposed(src1) && src1->ne[2]*src1->ne[3] > 1) {
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// KQ + KQV multi-batch
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ggml_cuda_mul_mat_batched_cublas(ctx, src0, src1, dst);
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} else if (use_dequantize_mul_mat_vec) {
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ggml_cuda_op_mul_mat(ctx, src0, src1, dst, ggml_cuda_op_dequantize_mul_mat_vec, nullptr);
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} else if (use_mul_mat_vec_q) {
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ggml_cuda_op_mul_mat(ctx, src0, src1, dst, ggml_cuda_op_mul_mat_vec_q, quantize_row_q8_1_cuda);
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} else if (use_mul_mat_q) {
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ggml_cuda_op_mul_mat(ctx, src0, src1, dst, ggml_cuda_op_mul_mat_q, quantize_mmq_q8_1_cuda);
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} else if (!split && src0->type == GGML_TYPE_F16 && (src1->type == GGML_TYPE_F16 || !any_gpus_with_slow_fp16)
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&& !ggml_is_transposed(src0) && !ggml_is_transposed(src1) && src1->ne[2]*src1->ne[3] > 1) {
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// KQ + KQV multi-batch without FlashAttention
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ggml_cuda_mul_mat_batched_cublas(ctx, src0, src1, dst);
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} else {
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ggml_cuda_op_mul_mat(ctx, src0, src1, dst, ggml_cuda_op_mul_mat_cublas, nullptr);
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}
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@ -146,23 +146,6 @@
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#define CC_RDNA2 (CC_OFFSET_AMD + 1030)
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#define CC_RDNA3 (CC_OFFSET_AMD + 1100)
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// define this if you want to always fallback to MMQ kernels and not use cuBLAS for matrix multiplication
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// on modern hardware, using cuBLAS is recommended as it utilizes F16 tensor cores which are very performant
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// for large computational tasks. the drawback is that this requires some extra amount of VRAM:
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// - 7B quantum model: +100-200 MB
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// - 13B quantum model: +200-400 MB
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//
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//#define GGML_CUDA_FORCE_MMQ
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// TODO: improve this to be correct for more hardware
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// for example, currently fails for GeForce GTX 1660 which is TURING arch (> VOLTA) but does not have tensor cores
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#if !defined(GGML_CUDA_FORCE_MMQ)
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#define CUDA_USE_TENSOR_CORES
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#endif
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#define MMVQ_MAX_BATCH_SIZE 8 // max batch size to use MMVQ kernels
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#define MMQ_MAX_BATCH_SIZE 64 // max batch size to use MMQ kernels when tensor cores are available
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#define MATRIX_ROW_PADDING 512 // last row of quant. matrices is a multiple of this to avoid out-of-bounds memory accesses
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#if defined(_MSC_VER)
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@ -343,15 +326,15 @@ static __device__ __forceinline__ half2 __shfl_xor(half2 var, int laneMask, int
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#define INT8_MMA_AVAILABLE
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#endif // !(defined(GGML_USE_HIPBLAS) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= CC_TURING
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static bool fast_fp16_available(const int cc) {
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static constexpr bool fast_fp16_available(const int cc) {
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return cc >= CC_PASCAL && cc != 610;
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}
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static bool fp16_mma_available(const int cc) {
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static constexpr bool fp16_mma_available(const int cc) {
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return cc < CC_OFFSET_AMD && cc >= CC_VOLTA;
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}
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static bool int8_mma_available(const int cc) {
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static constexpr bool int8_mma_available(const int cc) {
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return cc < CC_OFFSET_AMD && cc >= CC_TURING;
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}
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@ -643,19 +626,6 @@ struct ggml_cuda_type_traits<GGML_TYPE_IQ3_S> {
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static constexpr int qi = QI3_S;
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};
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static constexpr int get_mmq_x_max_host(int cc) {
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#ifdef CUDA_USE_TENSOR_CORES
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return cc >= CC_VOLTA && cc < CC_OFFSET_AMD ? MMQ_MAX_BATCH_SIZE : 64;
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#else
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return cc >= CC_VOLTA && cc < CC_OFFSET_AMD ? 128 : 64;
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#endif // CUDA_USE_TENSOR_CORES
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}
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// Round rows to this value for --split-mode row:
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static constexpr int get_mmq_y_host(int cc) {
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return cc >= CC_VOLTA ? 128 : 64;
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}
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//////////////////////
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struct ggml_cuda_device_info {
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@ -69,7 +69,13 @@ void ggml_cuda_op_mul_mat_q(
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GGML_UNUSED(src1_ddf_i);
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}
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bool ggml_cuda_supports_mmq(enum ggml_type type) {
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bool ggml_cuda_should_use_mmq(enum ggml_type type, int cc, int64_t ne11) {
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#ifdef GGML_CUDA_FORCE_CUBLAS
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return false;
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#endif // GGML_CUDA_FORCE_CUBLAS
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bool mmq_supported;
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switch (type) {
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case GGML_TYPE_Q4_0:
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case GGML_TYPE_Q4_1:
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@ -81,8 +87,32 @@ bool ggml_cuda_supports_mmq(enum ggml_type type) {
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case GGML_TYPE_Q4_K:
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case GGML_TYPE_Q5_K:
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case GGML_TYPE_Q6_K:
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return true;
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mmq_supported = true;
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break;
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||||
default:
|
||||
return false;
|
||||
mmq_supported = false;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!mmq_supported) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (int8_mma_available(cc)) {
|
||||
return true;
|
||||
}
|
||||
|
||||
if (cc < MIN_CC_DP4A) {
|
||||
return false;
|
||||
}
|
||||
|
||||
#ifdef GGML_CUDA_FORCE_MMQ
|
||||
return true;
|
||||
#endif //GGML_CUDA_FORCE_MMQ
|
||||
|
||||
if (cc < CC_OFFSET_AMD) {
|
||||
return cc < CC_VOLTA || ne11 < MMQ_DP4A_MAX_BATCH_SIZE;
|
||||
}
|
||||
|
||||
return cc < CC_RDNA3 || ne11 < MMQ_DP4A_MAX_BATCH_SIZE;
|
||||
}
|
||||
|
||||
@ -7,6 +7,8 @@
|
||||
#include <climits>
|
||||
#include <cstdint>
|
||||
|
||||
#define MMQ_DP4A_MAX_BATCH_SIZE 64 // Max. batch size to use for dp4a MMQ kernels when FP16 tensor cores are available.
|
||||
|
||||
typedef void (*load_tiles_mmq_t)(const char * __restrict__ x, int * x_tile, const int & kbx0, const int & i_max, const int & stride);
|
||||
typedef void (*vec_dot_mmq_t)(const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int & k0);
|
||||
typedef void (*mmq_write_back_t)(const float * __restrict__ sum, float * __restrict__ dst, const int & stride, const int & i_max, const int & j_max);
|
||||
@ -24,25 +26,42 @@ struct tile_x_sizes {
|
||||
int sc;
|
||||
};
|
||||
|
||||
// get_mmq_x_max_host is in common.cuh so that it can be used to determine the correct way to round for --split-mode row
|
||||
|
||||
static constexpr __device__ int get_mmq_x_max_device() {
|
||||
#if defined(GGML_USE_HIPBLAS) && defined(__HIP_PLATFORM_AMD__)
|
||||
return 64;
|
||||
static constexpr int get_mmq_x_max_host(const int cc) {
|
||||
return int8_mma_available(cc) ? 128 :
|
||||
#ifdef GGML_CUDA_FORCE_MMQ
|
||||
cc >= CC_VOLTA && cc < CC_OFFSET_AMD ? 128 : 64;
|
||||
#else
|
||||
#if __CUDA_ARCH__ >= CC_VOLTA
|
||||
#ifdef CUDA_USE_TENSOR_CORES
|
||||
return MMQ_MAX_BATCH_SIZE;
|
||||
#else
|
||||
return 128;
|
||||
#endif // CUDA_USE_TENSOR_CORES
|
||||
#else
|
||||
return 64;
|
||||
#endif // __CUDA_ARCH__ >= CC_VOLTA
|
||||
#endif // defined(GGML_USE_HIPBLAS) && defined(__HIP_PLATFORM_AMD__)
|
||||
cc >= CC_VOLTA && cc < CC_OFFSET_AMD ? MMQ_DP4A_MAX_BATCH_SIZE : 64;
|
||||
#endif // GGML_CUDA_FORCE_MMQ
|
||||
}
|
||||
|
||||
// get_mmq_y_host is in common.cuh so that it can be used to determine the correct way to round for --split-mode row
|
||||
static constexpr __device__ int get_mmq_x_max_device() {
|
||||
#ifdef INT8_MMA_AVAILABLE
|
||||
return 128;
|
||||
#else // INT8_MMA_AVAILABLE
|
||||
|
||||
#if defined(GGML_USE_HIPBLAS) && defined(__HIP_PLATFORM_AMD__)
|
||||
return 128;
|
||||
#else // defined(GGML_USE_HIPBLAS) && defined(__HIP_PLATFORM_AMD__)
|
||||
|
||||
#if __CUDA_ARCH__ >= CC_VOLTA
|
||||
#ifdef GGML_CUDA_FORCE_MMQ
|
||||
return MMQ_DP4A_MAX_BATCH_SIZE;
|
||||
#else // GGML_CUDA_FORCE_MMQ
|
||||
return 128;
|
||||
#endif // GGML_CUDA_FORCE_MMQ
|
||||
#else // __CUDA_ARCH__ >= CC_VOLTA
|
||||
|
||||
return 64;
|
||||
#endif // __CUDA_ARCH__ >= CC_VOLTA
|
||||
|
||||
#endif // defined(GGML_USE_HIPBLAS) && defined(__HIP_PLATFORM_AMD__)
|
||||
#endif // INT8_MMA_AVAILABLE
|
||||
}
|
||||
|
||||
static constexpr int get_mmq_y_host(const int cc) {
|
||||
return int8_mma_available(cc) || cc >= CC_VOLTA ? 128 : 64;
|
||||
}
|
||||
|
||||
static constexpr __device__ int get_mmq_y_device() {
|
||||
#if defined(GGML_USE_HIPBLAS) && defined(__HIP_PLATFORM_AMD__)
|
||||
@ -2590,4 +2609,4 @@ void ggml_cuda_op_mul_mat_q(
|
||||
const char * src1_ddq_i, float * dst_dd_i, const int64_t row_low, const int64_t row_high, const int64_t src1_ncols,
|
||||
const int64_t src1_padded_row_size, cudaStream_t stream);
|
||||
|
||||
bool ggml_cuda_supports_mmq(enum ggml_type type);
|
||||
bool ggml_cuda_should_use_mmq(enum ggml_type type, int cc, int64_t ne11);
|
||||
|
||||
@ -1,5 +1,7 @@
|
||||
#include "common.cuh"
|
||||
|
||||
#define MMVQ_MAX_BATCH_SIZE 8 // Max. batch size for which to use MMVQ kernels.
|
||||
|
||||
void ggml_cuda_op_mul_mat_vec_q(
|
||||
ggml_backend_cuda_context & ctx,
|
||||
const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst, const char * src0_dd_i, const float * src1_ddf_i,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user