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Removed WhiteSpaces
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@ -3823,13 +3823,13 @@ void ggml_vec_dot_q4_0_q8_0(int n, float * restrict s, size_t bs, const void * r
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svfloat32_t sumv1 = svdup_n_f32(0.0f);
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const int vector_length = ggml_sve_cnt_b*8;
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// VLA Implementation using switch case
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// VLA Implementation using switch case
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switch(vector_length)
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{
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{
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case 128:
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// predicate for activating higher lanes for 4 float32 elements
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const svbool_t pg =svptrue_pat_b32(SV_VL4);
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for (; ib + 1 < nb; ib += 2) {
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const block_q4_0 * restrict x0 = &x[ib + 0];
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const block_q4_0 * restrict x1 = &x[ib + 1];
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@ -3866,15 +3866,15 @@ void ggml_vec_dot_q4_0_q8_0(int n, float * restrict s, size_t bs, const void * r
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sumf = svaddv_f32(svptrue_b32(), svadd_f32_x(svptrue_b32(), sumv0, sumv1));
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break;
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break;
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case 256:
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case 256:
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// predicate for activating higher lanes for 16 int8 elements
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const svbool_t ptrueh_256 = svptrue_pat_b8(SV_VL16);
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// predicate for activating lower lanes for 16 int8 elements
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const svbool_t ptruel_256 = svnot_b_z(svptrue_b8(), ptrueh_256);
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for (; ib + 1 < nb; ib += 2) {
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const block_q4_0 * restrict x0 = &x[ib + 0];
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const block_q4_0 * restrict x1 = &x[ib + 1];
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@ -3904,14 +3904,14 @@ void ggml_vec_dot_q4_0_q8_0(int n, float * restrict s, size_t bs, const void * r
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sumf = svaddv_f32(svptrue_b32(), svadd_f32_x(svptrue_b32(), sumv0, sumv1));
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break;
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break;
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case 512:
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// predicate for activating higher lanes for 32 int8 elements
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const svbool_t ptrue = svptrue_pat_b8(SV_VL32);
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// predicate for activating higher lanes for 16 int8 elements
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// predicate for activating higher lanes for 16 int8 elements
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const svbool_t ptrueh = svptrue_pat_b8(SV_VL16);
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// predicate for activating lower lanes for 16 int8 elements from first 32 int8 activated lanes
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// predicate for activating lower lanes for 16 int8 elements from first 32 int8 activated lanes
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const svbool_t ptruel = svnot_b_z(ptrue, ptrueh);
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for (; ib < nb; ib += 2) {
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@ -3942,9 +3942,9 @@ void ggml_vec_dot_q4_0_q8_0(int n, float * restrict s, size_t bs, const void * r
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}
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sumf = svaddv_f32(ptrue, svadd_f32_x(ptrue, sumv0, sumv1));
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break;
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default:
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break;
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default:
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break;
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}
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@ -5403,20 +5403,20 @@ void ggml_vec_dot_q8_0_q8_0(int n, float * restrict s, size_t bs, const void * r
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const int vector_length = ggml_sve_cnt_b*8;
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//VLA Implemenation for SVE
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//VLA Implemenation for SVE
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switch(vector_length)
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{
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{
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case 128:
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// predicate for activating lanes for 16 Int8 elements
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svbool_t pg1 =svptrue_pat_b8(SV_VL16);
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svbool_t pg =svptrue_pat_b32(SV_VL4);
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for (; ib + 1 < nb; ib += 2) {
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for (; ib + 1 < nb; ib += 2) {
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const block_q8_0 * restrict x0 = &x[ib + 0];
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const block_q8_0 * restrict x1 = &x[ib + 1];
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const block_q8_0 * restrict y0 = &y[ib + 0];
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const block_q8_0 * restrict y1 = &y[ib + 1];
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// load x
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const svint8_t qx0_0 = svld1_s8(pg1, x0->qs);
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const svint8_t qx0_1 = svld1_s8(pg1, x0->qs+16);
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@ -5434,11 +5434,11 @@ void ggml_vec_dot_q8_0_q8_0(int n, float * restrict s, size_t bs, const void * r
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}
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sumf = svaddv_f32(pg, svadd_f32_x(pg, sumv0, sumv1));
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break;
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sumf = svaddv_f32(pg, svadd_f32_x(pg, sumv0, sumv1));
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break;
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case 256:
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//printf("sve256");
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//printf("sve256");
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for (; ib + 1 < nb; ib += 2) {
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const block_q8_0 * restrict x0 = &x[ib + 0];
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const block_q8_0 * restrict x1 = &x[ib + 1];
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@ -5452,24 +5452,24 @@ void ggml_vec_dot_q8_0_q8_0(int n, float * restrict s, size_t bs, const void * r
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// load y
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const svint8_t qy0 = svld1_s8(svptrue_b8(), y0->qs);
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const svint8_t qy1 = svld1_s8(svptrue_b8(), y1->qs);
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sumv0 = svmla_n_f32_x(svptrue_b32(), sumv0, svcvt_f32_s32_x(svptrue_b32(), svdot_s32(svdup_n_s32(0), qx0, qy0)), GGML_FP16_TO_FP32(x0->d)*GGML_FP16_TO_FP32(y0->d));
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sumv1 = svmla_n_f32_x(svptrue_b32(), sumv1, svcvt_f32_s32_x(svptrue_b32(), svdot_s32(svdup_n_s32(0), qx1, qy1)), GGML_FP16_TO_FP32(x1->d)*GGML_FP16_TO_FP32(y1->d));
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}
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sumf = svaddv_f32(svptrue_b32(), svadd_f32_x(svptrue_b32(), sumv0, sumv1));
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break;
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}
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sumf = svaddv_f32(svptrue_b32(), svadd_f32_x(svptrue_b32(), sumv0, sumv1));
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break;
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case 512:
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// predicate for activating high 256 bit
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// predicate for activating high 256 bit
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const svbool_t ptrueh = svptrue_pat_b8(SV_VL32);
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// predicate for activating low 256 bit
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// predicate for activating low 256 bit
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const svbool_t ptruel = svnot_b_z(svptrue_b8(), ptrueh);
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// predicate for activating high lanes for 8 float32 elements
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svbool_t asd = svptrue_pat_b32(SV_VL8);
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// predicate for activating low lanes for 8 float32 elements
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svbool_t dsa = svnot_b_z(svptrue_b32(), asd);
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svbool_t dsa = svnot_b_z(svptrue_b32(), asd);
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svfloat32_t sumv00 = svdup_n_f32(0.0f);
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@ -5480,9 +5480,9 @@ void ggml_vec_dot_q8_0_q8_0(int n, float * restrict s, size_t bs, const void * r
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const block_q8_0 * restrict y0 = &y[ib + 0];
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const block_q8_0 * restrict y1 = &y[ib + 1];
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//load 32 int8_t in first half of vector and put another 32 int8_t in second vector lower bits
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//load 32 int8_t in first half of vector and put another 32 int8_t in second vector lower bits
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// and add them to make one 64 element vector
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// load x
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// load x
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const svint8_t qx_32 = svld1_s8(ptrueh,x0->qs);
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svint8_t qx_64 = svld1_s8(ptruel,x0->qs+2);
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qx_64 = svadd_s8_x(svptrue_b8(), qx_32, qx_64);
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@ -5491,11 +5491,11 @@ void ggml_vec_dot_q8_0_q8_0(int n, float * restrict s, size_t bs, const void * r
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const svint8_t qy_32 = svld1_s8(ptrueh,y0->qs);
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svint8_t qy_64 = svld1_s8(ptruel,y0->qs+2);
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qy_64 = svadd_s8_x(svptrue_b8(), qy_32, qy_64);
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// scale creation
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// scale creation
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float32_t deq1= GGML_FP16_TO_FP32(x0->d)*GGML_FP16_TO_FP32(y0->d);
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float32_t deq2 = GGML_FP16_TO_FP32(x1->d)*GGML_FP16_TO_FP32(y1->d);
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// duplicate deq1 in first half of vector and deq2 in second half of vector
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svfloat32_t temp = svdup_f32_m(svdup_f32_z(asd, deq1), dsa,deq2);
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@ -5503,16 +5503,16 @@ void ggml_vec_dot_q8_0_q8_0(int n, float * restrict s, size_t bs, const void * r
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svfloat32_t sumvt = svdup_n_f32(0.0f);
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sumvt = svcvt_f32_s32_x(svptrue_b32(), svdot_s32(svdup_n_s32(0), qx_64, qy_64));
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sumv00 = svmla_f32_m(svptrue_b32(),sumv00,sumvt,temp);
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}
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sumf = svaddv_f32(svptrue_b32(), sumv00);
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sumf = svaddv_f32(svptrue_b32(), sumv00);
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break;
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default:
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break;
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default:
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break;
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}
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#elif defined(__ARM_NEON)
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