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metal : GGML_OP_RMS_NORM
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@ -642,6 +642,13 @@ typedef struct {
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int32_t ne1;
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int32_t ne1;
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uint64_t nb1;
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uint64_t nb1;
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} ggml_metal_kargs_mul_mv_id;
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} ggml_metal_kargs_mul_mv_id;
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typedef struct {
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int32_t ne00;
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int32_t ne00_4;
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uint64_t nb01;
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float eps;
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} ggml_metal_kargs_rms_norm;
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#endif
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#endif
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#endif // GGML_COMMON_DECL
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#endif // GGML_COMMON_DECL
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@ -2618,20 +2618,28 @@ static void ggml_metal_encode_node(
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float eps;
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float eps;
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memcpy(&eps, dst->op_params, sizeof(float));
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memcpy(&eps, dst->op_params, sizeof(float));
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id<MTLComputePipelineState> pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_RMS_NORM].pipeline;
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int nth = 32; // SIMD width
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int nth = 32; // SIMD width
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while (nth < ne00/4 && nth < 1024) {
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while (nth < ne00/4 && nth < (int) pipeline.maxTotalThreadsPerThreadgroup) {
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nth *= 2;
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nth *= 2;
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}
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}
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id<MTLComputePipelineState> pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_RMS_NORM].pipeline;
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nth = MIN(nth, ne00/4);
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ggml_metal_kargs_rms_norm args = {
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/*.ne00 =*/ ne00,
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/*.ne00_4 =*/ ne00/4,
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/*.nb01 =*/ nb01,
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/*.eps =*/ eps,
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};
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[encoder setComputePipelineState:pipeline];
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[encoder setComputePipelineState:pipeline];
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[encoder setBuffer:id_src0 offset:offs_src0 atIndex:0];
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[encoder setBytes:&args length:sizeof(args) atIndex:0];
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[encoder setBuffer:id_dst offset:offs_dst atIndex:1];
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[encoder setBuffer:id_src0 offset:offs_src0 atIndex:1];
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[encoder setBytes:&ne00 length:sizeof( int64_t) atIndex:2];
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[encoder setBuffer:id_dst offset:offs_dst atIndex:2];
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[encoder setBytes:&nb01 length:sizeof(uint64_t) atIndex:3];
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[encoder setBytes:&eps length:sizeof( float) atIndex:4];
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[encoder setThreadgroupMemoryLength:32*sizeof(float) atIndex:0];
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[encoder setThreadgroupMemoryLength:32*sizeof(float) atIndex:0];
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const int64_t nrows = ggml_nrows(src0);
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const int64_t nrows = ggml_nrows(src0);
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@ -1288,50 +1288,45 @@ kernel void kernel_norm(
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}
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}
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kernel void kernel_rms_norm(
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kernel void kernel_rms_norm(
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device const void * src0,
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constant ggml_metal_kargs_rms_norm & args,
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device float * dst,
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device const char * src0,
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constant int64_t & ne00,
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device char * dst,
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constant uint64_t & nb01,
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threadgroup float * shmem_f32 [[threadgroup(0)]],
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constant float & eps,
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uint tgpig[[threadgroup_position_in_grid]],
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threadgroup float * buf [[threadgroup(0)]],
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ushort tpitg[[thread_position_in_threadgroup]],
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uint tgpig[[threadgroup_position_in_grid]],
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ushort sgitg[[simdgroup_index_in_threadgroup]],
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uint tpitg[[thread_position_in_threadgroup]],
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ushort tiisg[[thread_index_in_simdgroup]],
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uint sgitg[[simdgroup_index_in_threadgroup]],
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ushort ntg[[threads_per_threadgroup]]) {
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uint tiisg[[thread_index_in_simdgroup]],
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if (sgitg == 0) {
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uint ntg[[threads_per_threadgroup]]) {
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shmem_f32[tiisg] = 0.0f;
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device const float4 * x = (device const float4 *) ((device const char *) src0 + tgpig*nb01);
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}
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float4 sumf = 0;
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device const float4 * x = (device const float4 *) (src0 + tgpig*args.nb01);
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float all_sum = 0;
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float sumf = 0.0f;
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// parallel sum
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// parallel sum
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for (int i00 = tpitg; i00 < ne00/4; i00 += ntg) {
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for (int i00 = tpitg; i00 < args.ne00_4; i00 += ntg) {
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sumf += x[i00] * x[i00];
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sumf += dot(x[i00], x[i00]);
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}
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}
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all_sum = sumf[0] + sumf[1] + sumf[2] + sumf[3];
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sumf = simd_sum(sumf);
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all_sum = simd_sum(all_sum);
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if (ntg > N_SIMDWIDTH) {
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if (sgitg == 0) {
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buf[tiisg] = 0.0f;
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}
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threadgroup_barrier(mem_flags::mem_threadgroup);
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threadgroup_barrier(mem_flags::mem_threadgroup);
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if (tiisg == 0) {
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if (tiisg == 0) {
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buf[sgitg] = all_sum;
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shmem_f32[sgitg] = sumf;
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}
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threadgroup_barrier(mem_flags::mem_threadgroup);
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all_sum = buf[tiisg];
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all_sum = simd_sum(all_sum);
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}
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}
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const float mean = all_sum/ne00;
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threadgroup_barrier(mem_flags::mem_threadgroup);
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const float scale = 1.0f/sqrt(mean + eps);
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device float4 * y = (device float4 *) (dst + tgpig*ne00);
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sumf = shmem_f32[tiisg];
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for (int i00 = tpitg; i00 < ne00/4; i00 += ntg) {
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sumf = simd_sum(sumf);
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const float mean = sumf/args.ne00;
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const float scale = 1.0f/sqrt(mean + args.eps);
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device float4 * y = (device float4 *) dst + tgpig*args.ne00_4;
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for (int i00 = tpitg; i00 < args.ne00_4; i00 += ntg) {
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y[i00] = x[i00] * scale;
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y[i00] = x[i00] * scale;
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}
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}
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}
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}
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