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[SYCL] fix the mul_mat_id ut issues (#8427)
* fix part of mul_mat_id * skip the bfloat 16 sycl ut Signed-off-by: Chen Xi <xi2chen@intel.com> --------- Signed-off-by: Chen Xi <xi2chen@intel.com> Co-authored-by: Meng, Hengyu <hengyu.meng@intel.com> Co-authored-by: Chen Xi <xi2chen@intel.com>
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@ -394,7 +394,7 @@ void ggml_backend_event_wait(ggml_backend_t backend, ggml_backend_event_t event)
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// backend registry
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#define GGML_REG_MAX_BACKENDS 16
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#define GGML_REG_MAX_BACKENDS 64
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struct ggml_backend_reg {
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char name[128];
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@ -3768,37 +3768,13 @@ static void ggml_sycl_mul_mat_id(ggml_backend_sycl_context & ctx, const ggml_ten
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stream->memcpy(ids_host.data(), ids_dev, ggml_nbytes(ids))));
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SYCL_CHECK(CHECK_TRY_ERROR(stream->wait()));
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const ggml_tensor_extra_gpu *src0_extra =
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(const ggml_tensor_extra_gpu *)src0->extra;
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const ggml_tensor_extra_gpu *src1_extra =
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(const ggml_tensor_extra_gpu *)src1->extra;
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const ggml_tensor_extra_gpu *dst_extra =
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(const ggml_tensor_extra_gpu *)dst->extra;
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ggml_tensor_extra_gpu src0_row_extra;
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ggml_tensor_extra_gpu src1_row_extra;
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ggml_tensor_extra_gpu dst_row_extra;
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ggml_tensor src0_row = *src0;
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ggml_tensor src1_row = *src1;
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ggml_tensor dst_row = *dst;
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src1_row.backend = GGML_BACKEND_TYPE_GPU;
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dst_row.backend = GGML_BACKEND_TYPE_GPU;
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src0_row.extra = &src0_row_extra;
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src1_row.extra = &src1_row_extra;
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dst_row.extra = &dst_row_extra;
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char *src0_original = src1->backend == GGML_BACKEND_TYPE_CPU
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? (char *)src0->data
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: (char *)src0_extra->data_device[ctx.device];
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char *src1_original = src1->backend == GGML_BACKEND_TYPE_CPU
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? (char *)src1->data
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: (char *)src1_extra->data_device[ctx.device];
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char *dst_original = dst->backend == GGML_BACKEND_TYPE_CPU
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? (char *)dst->data
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: (char *)dst_extra->data_device[ctx.device];
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char *src0_original = (char *)src0->data;
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char *src1_original = (char *)src1->data;
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char *dst_original = (char *)dst->data;
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src0_row.ne[2] = 1;
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src0_row.ne[3] = 1;
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@ -3827,12 +3803,9 @@ static void ggml_sycl_mul_mat_id(ggml_backend_sycl_context & ctx, const ggml_ten
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const int64_t i1 = id;
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const int64_t i2 = i12;
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src0_row_extra.data_device[ctx.device] =
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src0_original + i02*nb02;
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src1_row_extra.data_device[ctx.device] =
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src1_original + + i11*nb11 + i12*nb12;
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dst_row_extra.data_device[ctx.device] =
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dst_original + i1*nb1 + i2*nb2;
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src0_row.data = src0_original + i02*nb02;
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src1_row.data = src1_original + + i11*nb11 + i12*nb12;
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dst_row.data = dst_original + i1*nb1 + i2*nb2;
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ggml_sycl_mul_mat(ctx, &src0_row, &src1_row, &dst_row);
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}
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@ -3841,8 +3814,8 @@ static void ggml_sycl_mul_mat_id(ggml_backend_sycl_context & ctx, const ggml_ten
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ggml_sycl_pool_alloc<char> src1_contiguous(ctx.pool(), sizeof(float)*ggml_nelements(src1));
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ggml_sycl_pool_alloc<char> dst_contiguous(ctx.pool(), sizeof(float)*ggml_nelements(dst));
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src1_row_extra.data_device[ctx.device] = src1_contiguous.get();
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dst_row_extra.data_device[ctx.device] = dst_contiguous.get();
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src1_row.data = src1_contiguous.get();
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dst_row.data = dst_contiguous.get();
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for (int64_t i02 = 0; i02 < n_as; i02++) {
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int64_t num_src1_rows = 0;
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@ -3898,7 +3871,7 @@ static void ggml_sycl_mul_mat_id(ggml_backend_sycl_context & ctx, const ggml_ten
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});
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}
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src0_row_extra.data_device[ctx.device] = src0_original + i02*nb02;
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src0_row.data = src0_original + i02*nb02;
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GGML_ASSERT(nb11 == sizeof(float)*ne10);
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GGML_ASSERT(nb1 == sizeof(float)*ne0);
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@ -5221,6 +5194,10 @@ GGML_CALL static bool ggml_backend_sycl_supports_op(ggml_backend_t backend, cons
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return false;
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}
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}
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ggml_type src0_type = op->src[0]->type;
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if (src0_type == GGML_TYPE_BF16) {
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return false;
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}
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return true;
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} break;
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case GGML_OP_GET_ROWS:
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@ -5883,13 +5883,6 @@ static bool llm_load_tensors(
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auto & hparams = model.hparams;
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#ifdef GGML_USE_SYCL
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// disable MoE with SYCL until mul_mat_id is updated
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if (hparams.n_expert > 0) {
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n_gpu_layers = 0;
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}
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#endif
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model.split_mode = split_mode;
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model.main_gpu = main_gpu;
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model.n_gpu_layers = n_gpu_layers;
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